Senior design has been proceeding well! Here’s a quick update:
Note: I have not posted many design updates for the sake of protecting IP that has some solid market-potential.
While parts have been coming in, I did some additional LTSpice simulations of the Power Circuitry that I am designing–working to keep the output ripple below 3mV under all foreseeable loads. I have also been working on sourcing our parts, making sure to derate all specs to satisfy a good cushion beyond our derived requirements for factors such as noise and signal integrity. This was done as a secondary action to a big step in our project–the PCB!
Pulling an all-nighter, utilizing “Design for Manufacturing” tools, and riding my industry experience has led me to the ~7-sq-in. board (2.6″ x 2.7″) seen above (click for full-size):
The top is the LED driver, middle has Power Circuitry, bottom-left has the Sensing Block, and the right side has the Processing Block.
Special considerations were given to power and ground. I put polygons of copper wherever I could for these, and tried to minimize the return path for current. Vias were placed all over the place to ensure that current had the [seemingly] lowest inductance path to travel. Same goes for power, putting vias in place as needed to connect polygons. This was done especially when traces divided polygons/ground planes up.
When designing this, I had planned for 4 layers (Signal/VCC/GND/Signal) but realized that 2 layers would be sufficient (and save us money). For the second prototype, by utilizing four layers, the number of drill holes and vias would reduce, things could be a bit more compact, and power integrity would certainly improve due to shorter paths. I did not fully utilize the space on both sides of the board, but this was to try to make the bottom as flat as possible for a possible enclosure to be made.
Something exciting also happened recently. We won the Leung Student Venture Fund, and with it we have a fund to budget from to work on and prototype our project. We are very grateful of this chance to ensure we do not compromise on the hardware implementation of our first prototype.